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no-img_eng.gif  AN EFFICIENT, LOW RESOURCE, ARCHITECTURE FOR BACKPROPAGATION NEURAL NETWORKS
Pedro O. Domingos , Horácio C. Neto
no-img_eng.gif  FPGA Based Architecture for the Data Acquisition Electronics of the Clear-PEM System
J. Varela , P. Bento , C. Leong , I. C. Teixeira , J. P. Teixeira , J. Nobre , J. Rego , P. Lousã , P. Relvas , P. Rodrigues , A. Trindade
no-img_eng.gif  Re-configurable computing, Parameterized algorithms, Parameterized design methodology.
Aparna Nagargadde , Sridhar Gangadharpalli , Sridhar. V
no-img_eng.gif  PIPELINING SEQUENCES OF LOOPS: A FIRST EXAMPLE
Rui Rodrigues , João M. P. Cardoso
no-img_eng.gif  OPEN ARCHITECTURE HIERARCHICAL PLACEMENT FOR FPGA DATAPATH DESIGNS
Dong Kwan Kim , Cameron Patterson , Peter Athanas
no-img_eng.gif  OPTIMIZING AREA ON THE GENERATION OF SPECIFIC CIRCUITS IN FPGAS FOR SIMD APPLICATIONS
Germán León , José M. Claver , Germán Fabregat
no-img_eng.gif  A TEST INFRASTRUCTURE FOR COMPILERS TARGETING FPGAS
Rui M. M. Rodrigues , João M. P. Cardoso
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