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Title:
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PIPELINING SEQUENCES OF LOOPS: A FIRST EXAMPLE |
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Author(s):
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Rui Rodrigues , João M. P. Cardoso |
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ISBN:
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972-99353-8-6 |
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Editors:
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João M. P. Cardoso |
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Year:
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2005 |
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Edition:
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Single |
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Keywords:
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Pipelining, Mapping of Algorithms, Hardware Schemes, FPGAs. |
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Type:
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Workshop Paper |
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First Page:
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147 |
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Last Page:
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151 |
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Language:
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English |
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Cover:
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Full Contents:
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click to dowload 
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Paper Abstract:
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Sequences of loops or sets of nested loops exist in many applications. This paper shows a scheme to pipeline those sequences of loops in such a way that subsequent loops can start execution before the end of the previous ones. It uses a hardware scheme with decoupled and concurrent datapath and control units that start execution at the same time. The communication of data items between two loops in sequence is conducted by memories. Each element of one of such memories is responsible to flag the availability of the data requested by a subsequence loop. Thus, the control execution of subsequent loops is also orchestrated by data availability and out-of-order produced-consumed pairs are permitted. We apply the concept to a real example: a fast DCT algorithm. |
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