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Title:      FPGA Based Architecture for the Data Acquisition Electronics of the Clear-PEM System
Author(s):      J. Varela , P. Bento , C. Leong , I. C. Teixeira , J. P. Teixeira , J. Nobre , J. Rego , P. Lousã , P. Relvas , P. Rodrigues , A. Trindade
ISBN:      972-99353-8-6
Editors:      João M. P. Cardoso
Year:      2005
Edition:      Single
Keywords:      PEM, photoelectric event, Compton, hit, coincidence, DAE, DIGITSim, reconfigurable systems.
Type:      Workshop Paper
First Page:      131
Last Page:      138
Language:      English
Cover:      no-img_eng.gif          
Full Contents:      click to dowload Download
Paper Abstract:      The paper describes a reconfigurable architecture for the Data Acquisition Electronics (DAE) system of the Clear-PEM detector, which is a compact Positron Emission Mammography (PEM) detector for medical imaging with 12,288 channels aiming at high sensitivity and spatial resolution. The front-end system is based on a data-driven synchronous design that identifies and multiplexes the analog signals of channels above threshold and digitizes the data streams. The off-detector digital DAE system processes data that comes from the front end, and identifies the relevant one. Relevant data is afterwards transferred to a PC for image processing. To minimize dead-time, the DAE architecture makes extensive use of pipeline processing structures and of de-randomizer memories with multi-event capacity. The system operates at 100 MHz clock frequency and is capable of sustaining a data acquisition rate of 1 million events per second with efficiency above 95%, under a total single photon background rate in the detector of 10 MHz. The trigger and data acquisition logic is implemented in 8 large FPGAs with 4 million gates each and another 1.5 million gates FPGA. A software model of the entire PEM system has been used in a Monte Carlo simulation environment in order to generate test benches and to verify system efficiency. Results of simulation are compared with VHDL hardware simulation results in order to validate hardware system design. The most significant aspects of hardware implementation are provided.
   

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