|
Title:
|
SAFETY-RELATED COMPUTERIZED EMBEDDED SYSTEMS WITH HETEROGENOUS REDUNDANCY |
|
Author(s):
|
Joseph Khattar, Eike Hahn, Samer Telawi, Michael Schwarz and Josef Boercsoek |
|
ISBN:
|
978-989-8704-42-9 |
|
Editors:
|
Yingcai Xiao, Ajith Abraham, Guo Chao Peng and Jörg Roth |
|
Year:
|
2022 |
|
Edition:
|
Single |
|
Keywords:
|
Safety-Related Computerized Systems, Redundant Computing, Safety System on Chip, Functional Safety |
|
Type:
|
Full Paper |
|
First Page:
|
176 |
|
Last Page:
|
184 |
|
Language:
|
English |
|
Cover:
|
|
|
Full Contents:
|
click to dowload 
|
|
Paper Abstract:
|
Recent advancements in the embedded systems field have resulted in more complicated systems with application-specific blocks (IP cores), often known as System on Chip (SoC) devices. Several redundancy-based embedded designs provide reliability and safety for SoC in aeronautics, automotive, industrial automation, railway, and space. In this paper, a Safety System-on-Chip heterogenous1oo2 architecture is presented. The design is based on two open-source and proven in-use cores, LEON3 from Cobham Gaisler and RISCV processors SweRV EH1 from Western Digital. The SoC is implemented on a Xilinx FPGA system and supplemented with conventional peripherals from the Xilinx IP library and Cobham Gaisler. A software comparator is included for a diagnostic. Each core has independent IPs, and the software comparator evaluates data from both cores; in case of deviation, the system is rendered to an energized safe state. |
|
|
|
|
|
|
Digital Library 
