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Title:
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EVALUATION OF INSTRUCTION SETS FOR SUPERSCALAR EXECUTION |
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Author(s):
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Virginia Escuder Cabañas , Raúl Durán Díaz , Rafael Rico López |
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ISBN:
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972-8924-09-7 |
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Editors:
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Nuno Guimarães, Pedro Isaías and Ambrosio Goikoetxea |
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Year:
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2006 |
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Edition:
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Single |
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Keywords:
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Instruction Set Architecture, Instruction level Parallelism, Graph Theory. |
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Type:
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Short Paper |
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First Page:
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452 |
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Last Page:
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456 |
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Language:
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English |
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Cover:
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Full Contents:
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click to dowload 
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Paper Abstract:
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Instruction set design is a fundamental aspect of computer architecture. A critical requirement of instruction sets design is to allow for concurrent execution, avoiding those constructs that may produce data dependencies. Therefore, it is important to count on methods and tools for the evaluation of the behavior of instruction sets and quantify the influence of particular features of its architecture into the overall available parallelism. We propose an analysis method that applies graph theory to gather metrics and evaluate the impact of different characteristics of instruction sets as sources of coupling, quantifying available parallelism. We present a case study using the x86 instruction set and obtain some measures of the influence of condition flags in code coupling. |
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