|
Title:
|
An Optimized FPGA Implementation of an AES Algorithm for Embedded Applications |
|
Author(s):
|
Ting Liu , Camel Tanougast , Philippe Brunet , Yves Berviller , Hassan Rabah , Serge Weber |
|
ISBN:
|
972-99353-8-6 |
|
Editors:
|
João M. P. Cardoso |
|
Year:
|
2005 |
|
Edition:
|
Single |
|
Type:
|
Workshop Paper |
|
First Page:
|
111 |
|
Last Page:
|
118 |
|
Language:
|
English |
|
Cover:
|
|
|
Full Contents:
|
click to dowload 
|
|
Paper Abstract:
|
The run time reconfiguration (RTR) temporal partitioning can be applied to the reconfigurable embedded system design in order to optimize an implementation. In this paper we present the implementation of an Advanced Encryption Standard (AES) algorithm (128 bit Key length) for embedded applications. The goal of this work is to segment the execution of an application in order to reduce the reconfigurable logic surface which is necessary for its implementation. The originality of this implementation is that, it combines RTR implementation with an architectural solution (AS) based on the reuse of the operators. This work allows obtaining a compromise between the smallest reconfigurable logical area and enough throughputs rate for low-end embedded applications. An implementation on a Xilinx Virtex FPGA device uses only 425 CLB slices and our FPGA implementation reaches a throughput of 205 Mbps at a clock frequency of 77.8 MHz. |
|
|
|
|
|
|
