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Title:
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ADOPTING THE SMALL-WORLD NETWORK IN ROUTING STRUCTURE OF FPGA |
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Author(s):
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Masahiro Iida , Shinya Abe , Hisashi Tsukiashi , Ryoji Ogata , Toshinori Sueyoshi |
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ISBN:
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972-99353-8-6 |
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Editors:
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João M. P. Cardoso |
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Year:
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2005 |
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Edition:
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Single |
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Keywords:
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Routing Structure, Reconfigurable Logic, FPGA, Small-World Network, Programmable Logic. |
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Type:
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Workshop Paper |
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First Page:
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92 |
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Last Page:
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98 |
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Language:
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English |
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Cover:
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Full Contents:
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click to dowload 
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Paper Abstract:
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The degree of integration and operating frequency of programmable logic has improved dramatically with the development of process technology. However, within the deep sub-micron process, the delay, reliability, cost, and power tend to be determined by interconnections. If this wiring delay under the deep sub-micron process is not considered, then speedup cannot be expected. This paper proposes a novel routing structure using a Small World Network structure for the interconnection of reconfigurable logic. This report demonstrates that by optimizing the segment length of wires and reducing the number of switches, the total delay on a signal path can be reduced. As a result of evaluation, the average number of switches between the arbitrary switch blocks confirmed a reduction of about 10 - 14% when using the Small World Network structure. |
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