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Title:
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A RISC ARCHITECTURE EXTENDED BY AN EFFICIENT TIGHTLY COUPLED RECONFIGURABLE UNIT |
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Author(s):
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N. Vassiliadis , N. Kavvadias , G. Theodoridis , S. Nikolaidis |
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ISBN:
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972-99353-8-6 |
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Editors:
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João M. P. Cardoso |
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Year:
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2005 |
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Edition:
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Single |
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Keywords:
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RISP, RFU, tightly-coupled,
coarse-grain. |
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Type:
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Workshop Paper |
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First Page:
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41 |
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Last Page:
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49 |
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Language:
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English |
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Cover:
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Full Contents:
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click to dowload 
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Paper Abstract:
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The architecture of an embedded processor extended with a tightly coupled coarse grain Reconfigurable Functional Unit (RFU) is proposed. The efficient integration of the RFU with the control unit and the datapath of the processor eliminates the communication overhead between them. To speed up execution the RFU exploits Instruction Level Parallelism (ILP) in addition with spatial computation. Also, the proposed integration of the RFU can more efficiently exploit the processors pipeline structure leading to even further performance improvements. The architecture model was synthesized with a 0.13um process and a demonstration application was executed. Results prove performance improvements in addition with potentially reduced energy consumption. |
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