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Title:
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A LEARNING MANAGEMENT SYSTEM DESIGNED FOR A BASIC LABORATORY COURSE ON COMPUTERARCHITECTURE |
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Author(s):
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Eladio Gutiérrez , Julián Ramos , Sergio Romero , María A. Trenas |
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ISBN:
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978-972-8924-42-3 |
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Editors:
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Miguel Baptista Nunes and Maggie McPherson (series editors: Piet Kommers, Pedro Isaías and Nian-Shing Chen) |
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Year:
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2007 |
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Edition:
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V I, 2 |
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Keywords:
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Computer architecture, laboratory work, VHDL, schematic, automatic evaluation and assessment |
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Type:
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Full Paper |
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First Page:
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68 |
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Last Page:
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75 |
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Language:
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English |
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Cover:
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Full Contents:
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click to dowload 
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Paper Abstract:
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Design and simulation of digital circuits is an important issue in the computer engineering curricula. Usually, laboratory
assignments consist of the implementation of certain HW specifications involving the use of CAD tools with a schematic
or VHDL design entry. A basic course on computer architecture, an essential issue in the computer science curricula, is
just a particular case. We have implemented a web-based learning management system (LMS) supporting this kind of
practical content. From the teachers point of view, one of the key elements of the system is the automatic checking and
evaluation engine that keeps the information about the current state of students work always up to date. This allows a
quicker feedback from teachers to students, as the system also provides automatic assessment to a certain extent. Without
this engine, this task becomes very time consuming, specially when there is a high number of students. As for the
students, it is intended to go beyond the mere hosting, bringing them the opportunity of knowing at all instances the
status of their lab work, regardless of their working at home or at the laboratory. Most tools used on the implementation
of our LMS are easily available and free. Additionally this LMS is extendable or portable to other subjects related to the
digital circuit design. |
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